Library/Chip Designer and Engineering Manager
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Engineer *.      36, married, 1 child, Russian citizenship.
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EXPERIENCE:        12 years in development and project/team management of 
                   silicon libraries and EDA tools integration.

# ASIC Libraries:  7 years in Std. cells, I/O, Memories and Testchip project 
                   management for the COMPASS/Avant!/Synopsys 0.5, 0.35, 
                   0.25, 0.18, 0.13um and 90nm technologies.

# SC Design:       SC library design including development of flow for 
                   optimisation, characterisation, validation and EDA tools 
                   integration and qualification.

# Memory Design:   memory design(2-port RAM, ROM, VROM, SRAM) including
                   compiler development, EDA tools integration and qualification.

# I/O Design:      design of staggered I/O and PCI I/O pad libraries.

# Testchip Design: design of functioanl/perfomance testchip for SC and I/O silicon validation.

# CPU Design:      2 years in physical implementation of IA64 compatible cores, 
                   icluding design flow piloting and testing for 65 and 45nm technologies.

# Team management: More than 10 years in project/team management in library/chip design.

# EDA Tools:       Apollo/Astro, Star-RC, Hercules, Hspice, Cosmos, Mars-Rail, Mars-Xtalk,
                   Star-Sim, Star-MTB, Synopsys LC/DC/PC/PT/PT-SI/VCS/ICC,
                   Formality, Cadabra, ModelSim, Calibre, Silvaco Celebrity/Expert/SmartSpice.

# Programming:     C, Perl, JavaScript, Mainsail.

# Objective:       Share and improve my library knowledge and to ensure customer success by
                   close customer relationship and a professional support.
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