PERSONAL
Name: Oleg S. SEVALNEV.
Age: was born in 1971 in Moscow, Russia.
Martial status: married, one child.
Languages: native Russian, English.
Email: oleg_sevalnev@mail.ru.
Summary:
Engineering Manager with broad and extensive background
in ASIC cell library development, microprocessors implementation
and design flow support.
EXPERIENCE
Skills:
Digital circuit design and simulation,
Custom layout and physical verification,
Std. cell and memory compiler libraries developing and verification,
Chip and library Design flow creation and support,
Engineering team management.
Technologies: 0.5um-45nm
Modeling Languages:
VHDL (Vital & nonVital), Verilog (SDF & nonSDF), SDF,
Synopsys Liberty, Avant! Apollo CLF,
Behavioral Modeling Language of COMPASS,
SDL of Silvar-Lisco.
CAD Packages:
"COMPASS ASIC Design Tools",
"Sagantec DREAM compactor",
"Avant! tools (Hercules DRC & LVS,
Star-RC, HSpice, Star-Sim, Polaris, Milkyway,Astro,
Star-MTB, Chrysalis formal verification)",
"IKOS Voyager",
"HILO system",
"Mentor (ModelSim, Calibre, Opus)",
"CADENCE (Dracula, Leapfrog, Verilog-XL, Abstract, SOC Encounter, Conformal)",
"Synopsys tools (PrimeTime/PrimeTimeSI, VCS, PrimePower, Formality,
Cadabra, library/design/test compilers, ICC, Liberty Screener)",
"Silvaco tools (Celebrity/Expert, Scholar, SmartSpice)",
"Silicon Metrics (cellRater)",
"Intel internal tools".
Programming Languages and Environments:
C, Perl, C-shell, AWK, JavaScript, Mainsail, ClearCase.
Operating System and Applications:
Solaris, Red Hat, MS Windows, MS-DOS, VAX VMS.
OpenOffice, Microsoft Office (Project, Word, Excel, PowerPoint, Sharepoint, FrontPage),
FrameMaker, Acrobat Reader, Mozilla.
EMPLOYMENT
03.1994-02.1995:
Was in the staff of Microelectronics Research Institute "PROGRESS" in
Moscow. Was employed as an engineer-programmer.
Subject: creation the system for the logic data translating.
Expertise: C programming, CAD logic data formats, logic and fault
modeling and simulation, automatic test vector generation.
03.1995-08.1995:
Was in the staff of "COMPASS Design Automation Inc." in
Sophia-Antipolis in France. Was employed as an ASIC
library designer.
Subject: ASIC libraries (Std cells, embedded ROMs/RAMs/multipliers)
design.
New Expertise: layout design, ISM & Prop/Ramp & look-up table timing
characterisation, logic and analog simulation,
datasheet generation.
Trainings: "Compass ASIC Design Tools", "Compass Library
development flow", "ISM(input-slope model) Characterisation".
Projects: "0.5um Metal Programmable ROM Compiler (designer)",
"0.5um Multiplier Compiler (designer)",
"0.5um High Perf Sync RAM (designer)"
09.1995-04.1996:
Was in the staff of Microelectronics Research Institute "PROGRESS" in
Moscow. Was employed as an ASIC library designer.
Subject: ASIC libraries (Std cells, embedded ROMs & RAMs,
DataPath) design for "COMPASS".
New Expertise: layout design, ISM characterisation,
datasheet generation, web page design, javascript programming.
Projects: "0.6um 3v Poly Input Std. Cell Library (designer)",
"Intranet Site creating"
05.1996-01.2004:
Was in the staff of MCST.
Was employed as an ASIC library designer.
Subject: ASIC libraries (Std cells, embedded ROMs & RAMs, DataPath)
design for "Avant!" / "Synopsys".
New Expertise: layout design, layout design rule deck design,
physical verification, look-up table timing
characterization, logic and analog simulation,
static-timing analysis with/without noise,
datasheet generation, formal verification, testchip design,
place and route, perl scripting, library QA.
Trainings: "LQS(library qualification system)", "MTB(master tool box)"
Projects: "Two-Port RAM Vital VHDL model",
"0.25um Async. Two-Port Ram Compiler (project leader)",
"0.25um Async. Two-Port Ram Compiler (project leader)",
"0.25um Optimum Silicon Std Cell Library",
"Library deliverables QA flow",
"Memory Compiler Power Characterisation flow",
"0.18um Staggered Pad I/O Library (project leader)",
"0.18um PCI Pad I/O Library (project leader)",
"0.13um Optimum Silicon Std. Cell Library (project leader)",
"0.13um Fast Silicon Std. Cell Library (project leader)",
"0.13um Functional/Perfomance Fast Silicon Std. Cell Testchip".
02.2004-03.2005:
Was assigneed as a library team manager.
Subject: ASIC libraries (Std. cells, I/O) design
for "Virtual Silicon".
New Expertise: project/team management/planning, LEF generation,
Calibre DRC deck, FastScan models.
04.2005-04.2006:
Was in the staff of ZAO "Intel A/O".
Was employed as senior hardware engineer.
Subject: Design implementation.
New Expertise: Design automation, microprocessor architecture,
logical&physical implementation, floorplanning,
static timing analysis.
Projects: 65/45nm physical implementation of IA64 CPU.
05.2006-12.2007:
Was assigned as engineering manager at Intel.
Subject: People management, design implementation.
New Expertise: Goal setting, project scheduling, resourse allocation,
risk taking, team development, design automation.
Projects: 45nm physical implementation of IA64 CPU.
EDUCATION
Received an engineering education from Moscow Institute of
Radioengineering, Electronics and Automation, department
of cybernetics, specialized in the design and technology
of electronic-calculating apparatures. Had received the diploma
of engineer-designer of electronic systems in 1994 year.
Successfuly completed the Intel university technical courses
"Layout, Silicon Test & Debug", "Logic & Circuit Design",
"Intro to Microprocessors" and non-technical "Constructive
Confrontation", "Effective Meetings", "Structured Problem Solving",
"Effective Listening", "Strengthening Manager Skills", "Stakeholder
Management", "Management and Leadership Expectations", "Setting
Clear and Mutual Expectations"
AWARDS
Have COMPASS certificates of Outstanding Accomplishment
for successfully completed the development of the
"PASSPORT 0.6 micron 3 Volt Poly Input Standard Cell Library",
"PASSPORT 0.5 micron 3 Volt Synchronous RAM library",
"PASSPORT 0.5 micron 3 Volt Dual Port RAM library",
"PASSPORT 0.5 micron 5 Volt High Density Datapath library",
"PASSPORT 0.5 micron libraries V9 testing".
Intel department award "in recognition of valuable contribution
in completing CDR0 pilots for SDP fubs".