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See my Short and Full summaries for more details about my working experience. View Oleg Sevalnev's profile on LinkedIn

I spent 10 years in the ASIC library development. So, on this page I collect the list of LibDev related sites. Use it on your own risk.

Library Developers

Company Type Fndr. Tech. About
AMI Semiconductor SC, IO, Mem, PLL, IP AMI 0.5, 0.35, 0.18, 0.13 AMIS designs, develops and manufactures a broad range of integrated mixed-signal products.
ARM SC, IO, Mem, IP 1st Silicon, Chartered, DongbuAnam, Grace, HHNEC, HeJian, IBM, MagnaChip, SMIC, Samsung, Silterra, TSMC, Tower, UMC, Vanguard 0.25, 0.18, 0.16, 0.15, 0.13, 0.11, 90, 80, 65 The ARM® product family of Artisan® Physical IP solutions provide the building blocks to create highly optimized System-on-Chip (SoC) designs. 
Atmel SC, IO, Mem, IP Atmel 0.60, 0.35, 0.25, 0.21, 0.18, 0.13, 90 Atmel’s in-house process technology development teams work closely with the product design engineers to ensure that process technology matches product requirements. The result is a rich menu of advanced process options that give every product its edge in terms of performance, power consumption and die size.
Dolphin Technology SC, IO, Mem, IP TSMC, IBM, UMC 0.25, 0.18, 0.13, 90, 65 Dolphin Technology, Inc. provides a wide range of High Performance, High Speed, Low-Power Silicon IP (SIP).
Faraday Technology SC, IO, MEM, IP UMC 0.5, 0.35, 0.18, 0.13, 90, 65 Faraday Technology Corporation is a leading fabless ASIC vendor as well as a silicon intellectual property (SIP) provider.
Fujitsu SC, IO, Mem, IP Fujitsu 0.18, 0.11, 90 Fujitsu Standard cell product are based on our leading edge CMOS process technologies. Utilizing multiple Vth transistors and libraries targeted for density, power or performance, the design implementation can be performed to exactly meet the customer requirements.
GlobalCAD, Inc SC, IO, Mem, IP 1st Silicon, Chartered, HHNEC, Silterra, SMIC, TSMC, UMC 0.6, 0.5, 0.35, 0.18, 0.15, 0.13 Focusing on high performance and low cost system-on-a-chip solutions for highly integrated embedded systems, GlobalCAD, Inc. is a world-class provider of complete front-end to back-end services.
GLOBAL UNICHIP IO, Mem, IP TSMC 0.35, 0.25, 0.18, 0.13 Global Unichip Corp. (GUC), a dedicated one-stop, full service SoC (System On Chip) Design Foundry.
Goyatek Technology Mem, IP TSMC 0.35, 0.25, 0.18 Goyatek Technology Inc. provides flexible Analog / Digital Semiconductor Intellectual Properties (SIP) components and Sourcing Service, including In-house IPs and 3rd Party IPs.
IPLib Mem, IP TSMC, SMIC, VIS, GSMC, X-Fab 0.25, 0.18 Intellectual Property Library Company (IPLib) provides the customers with the most competitive IPs to better their profits. These include memory compliers, customized memory macros, power management IPs, clock IPs, data conversion IPs, and interface IPs.
Kilopass Mem TSMC 0.18 Kilopass Technology Inc develops and markets advanced embedded non-volatile memory (NVM) technology, manufactured in standard logic CMOS processes.
MOSAID Technologies SC, IO, Mem, IP TSMC, UMC 0.25, 0.18, 0.15, 0.13, 90 MOSAID is a global leader in semiconductor technology, serving its customers with innovative intellectual property and memory test system products and services.
MoSys Mem TSMC, Chartered, SMIC 0.13, 90 MoSys Inc. is the leader in high-density embedded memory IP for system-on-chip (SoC) applications.
Novelics Mem     Whether your SoC requires embedded 6T or 1T based SRAM, high speed Cache, Register File, ROM, FLASH, or CAM, Novelics' advanced memory compiler technology generates high performance, optimized memory blocks that will exceed your design performance and time to profit requirements.
Samsung SC, Mem, IO, IP Samsung 0.35, 0.25, 0.18, 0.13, 90  
SMIC SC,IO SMIC 0.35, 0.25, 0.18, 0.15, 0.13, 90 Featuring different pad pitch, different voltage and programmable I/O, these silicon-proven and production-ready libraries are, in many ways, the most economical I/O solutions needed for today's cost-sensitive industrial environments and applications.
Synopsys SC, IO, Mem, IP TSMC, Chartered, Tower 0.35, 0.25, 0.18, 0.15, 0.13, 90, 65 Synopsys partners with industry leading foundries to provide designers with easily accessible, silicon proven standard cells, I/Os and memories, which are optimized for their process technology.
Tanner CES SC, IO, Mem, IP Analog Devices, AMI, AMS, Chartered, China Huajing, HP, Huindai, IBM, Mietec-Alctel, Mitel, NSA, National Semiconductor, Peregrine, Supertec, Symbios, Tower, TSMC, UMC, Temic, Sandia, 0.8 - 90 Tanner Consulting & Engineering Services designs quality, high-performance ASIC and VLSI solutions for its clients through contracted design and development efforts, consulting services, field engineering and training programs.
TSMC SC, IO, Mem, IP TSMC 0.5, 0.35, 0.25, 0.18, 0.15, 0.13, 90, 65 TSMC offers high performance library services, including in-house library services and third party library services.
UniRAM Technology Mem   0.13 UniRAM Technology, Inc. designs, develops, and licenses high performance memory solutions.
VeriSilicon SC, IO, Mem, IP SMIC, GSMC, ASMC, HHNEC, HJTC 0.6, 0.35, 0.25, 0.18, 0.15, 0.13 VeriSilicon's Standard Design Platforms (SDP) including standard cell libraries, I/O cell libraries, and memory compilers, are optimized specifically for the wafer foundries in China.
Virage Logic SC, Mem, IO Chartered, Dongbu Electronics, IBM, Silterra, SMIC, Tower, TSMC, UMC 0.25, 0.18, 0.15, 0.13, 0.12, 0.11, 90 Virage Logic Corporation  rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits.

LibDev Specific Software

Company Layout Characterization Optimization Verification
Altos Design Automation   Liberate    
Cadence   SignalStorm (tutorial)    
Fenix Design Automation       Crossfire
Legend Design Technology   CharFlo-Memory    
Library Technologies   LibChar CellOpt, LowSkew  
Magma Design Automation   SiliconSmart    
Nangate Library Creator Library Creator, Library Characterizer Library Creator Library Creator, Liberty Analyzer
Prolific ProGenesis      
Radix Tools   xlicdsm   Std. cell library characterization.
Sagantec SiClone, SiFix   SiFix, DFM-Fix  
SIMUCAD Design Automation   AccuCell    
Synopsys Cadabra Liberty NCX Circuit Explorer Liberty parser, Liberty screener, Library Compiler
VeriPool   GSpice (free)    
Z Circuit   ZChar   Library Analyzer
Zenasis Technologies     ZenTime-CT  

LibDev Papers

Name Abstract
Papers on BIST Various papers on embedded memory BIST architectures.
Standard Cell Library Design This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design.
Improving Cell Libraries for Synthesis This paper examines the issues associated with building a cell library that will serve as the target for an automated synthesis tool and particularly focuses on cell library modifications that will improve the speed of a circuit. A number of library modifications are suggested here, and an experimental method for evaluating their effectiveness is described. This method is then used to quantify the importance of each modification as clearly as possible. The conclusion of this work is that relatively simple modifications in a cell library can lead to 20-30% improvements in final circuit speed, and that the principles motivating these modifications are not embodied in the cell sets of most commercial ASIC libraries.
High Yield Std Cell Libraries: Optimization and Modeling In this paper, we present a flow for architecting standard cell libraries in nanometer technologies. The proposed approach relies on a Yield Characterization Environment to evaluate a set of manufacturability metrics and analyze multiple design trade-offs. We have identified four classes of manufacturability objectives that we addressed in our standard cell architectures: Average Functional Yield, Functional Yield Consistency, Performance Consistency and Leakage. Cells optimized for different manufacturability objectives present different trade-offs and require different layout architectures. We will show examples of such different trade-offs and architectural requirements and show the impact of adopting high-manufacturability standard cells on product Yields.
Optimized power-delay curve generation for standard cell ICs An effective way to compare logic techniques, logic families, or cell libraries is by means of power (or area) versus delay plots, since the efficiency of achieving a particular delay is of crucial significance. In this paper we describe a method of producing an optimized power versus delay curve for a combinational circuit.
Optimal P/N Width Ratio Selection for Standard Cell Libraries The main contribution of this paper is the development of a theoretical framework through which library designers can determine “optimal” P/N width ratio for each logic gate in their high-performance standard cell library. This theoretical framework utilizes new gate delay models that explicitly represent the dependence of delay on P/N width ratio and load. These delay models yield highly accurate delay for CMOS gates in a 0.12um Leff deep-submicron technology.
Under the Hood of Library IP Little-known aspects of library design that can directly impact the time to market, design flow complexity, and NRE cost of your next project.
An alternative logic approach to implement high-speed low-power full adder cells This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs.
Design-specific standard cells yield custom performance Various methodologies for use of design-specific cells have been presented in this article. These range from simple cell substitution from compatible libraries, if they exist, to creation of design-specific macro cells for special datapath design techniques, to general on-the-fly creation of design-specific cells for more general types of design.
Gate-size selection for standard cell libraries This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is defined to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement.
OASIS vs. GDSII Stream Format Efficiency The OASIS format was designed to be a replacement for the GDSII stream format. Previous papers have reported that OASIS files can be 5-20X smaller than comparable GDSII files. This paper examines the storage capabilities of OASIS, as well as other benefits, in more detail.
Impact of process variations on the alpha-particle-induced SER of emdedded SRAMs We investigate the spread in soft-error rate owing to variations in the process parameters. We show that the use of the high-Vt process option can reduce SER, because of a decrease in the collection of induced charges.

LibDev Vendor Docs

Name Abstract
ASIC Design Guidelines The Atmel ASIC Design Guidelines constitute a general set of recommendations intended for use by designers when preparing circuits for fabrication by Atmel. The guidelines are independent of any particular CAD tool or silicon process. It may be useful for library designers as well.
Liberty CCS Timing This document describes the Synopsys CCS Timing model for accurate and efficient cell-level delay calculation.
Liberty CCS Noise This document describes the Synopsys CCS Noise model for cell-level noise analysis.
Liberty CCS Power This document describes the Synopsys CCS Power model for advanced power and rail analysis and power optimization.
Motivation and Methodology for Nanometer Library Characterization This paper discusses the need for more advanced library characterization – and library characterization tools – for nanometer designs. This paper outlines best practices for library characterization, and provides examples of the impact of characterization technique on delay-calculation accuracy.

LibDev Formats and Standards

Name Abstract
ALF at  IEEE 1603 IEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks.
CIF The Caltech Intermediate Form is a means of describing graphic items of interest to LSI circuit and system designers.
Effective current source model The effective current source model (ECSM) is a very accurate delay model designed to solve this key industry problem—how to accurately model delay under different voltage scenarios.
GDSII Stream GDSII format description.
IBIS IBIS is a standard for electronic behavioral specification of integrated circuit input/output analog characteristics.
OASIS Open Artwork System Interchange Standard. This format is designed primarily to encapsulate hierarchical mask layout for interchange between EDA systems. Replacement for GDSII stream.
UPF Unified Power Format - an open, language-independent, comprehensive standard for the specification of power-aware requirements, design intent, implementation, verification and analysis across all levels of design abstraction.
Vital VHDL IEEE Std 1076.4-2000 for VITAL ASIC Modeling Specification.
VSIA IP Tagging The VCID standard provides semiconductor foundries and providers of intellectual property (IP) with an automated and succinct means to track the use of IP cores into the fabrication processes. This is accomplished through the use of tracking information embedded by IP providers or users into the Graphical Design System II-Stream (GDSII-Stream) file. This standard addresses the tracking of IPs into the mask-making portion of the fabrication processes.

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This site was last updated 05/13/08